1) Field of the Invention
The present invention relates to a technology for predicting a warp of a printed-wiring-board efficiently.
2) Description of the Related Art
In recent years, in accordance with a reduction in thickness of a printed-wiring-board used in electronic apparatuses such as a personal computer and a cellular phone and an increase in a density of a wiring pattern, a problem due to warp of a printed-wiring-board occurs. Therefore, it is necessary to predict warp that occurs in a printed-wiring-board and, when occurrence of warp to be a problem is predicted, take measures like examination of a reinforcement structure for the printed-wiring-board and change of a layout of components in advance.
As a method of predicting warp that occurs in a printed-wiring-board, there are a method of producing a printed-wiring-board in advance, applying a test to the produced printed-wiring-board, and verifying a problem related to warp of the board (prototype evaluation) and a method of modeling wiring patterns of a printed-wiring-board and predicting warp of the board using a simulation technique like a finite element method. Note that, in Japanese Patent Application Laid-Open No. 2002-230047, an algorithm like a quadtree area division is implemented for wiring patterns to make it possible to perform a thermal analysis calculation related to the printed-wiring-board.
However, in the conventional technology, there is a problem in that it is impossible to predict warp of a printed-wiring-board efficiently.
For example, prediction of warp of a printed-wiring-board by the prototype evaluation can carry out verification concerning warp only after all steps from designing to manufacturing of the printed-wiring-board are completed. Therefore, time and cost for the verification are enormous.
In addition, when verification of warp is carried out using a simulation such as the finite element method, modeling of a printed-wiring-board is required. With a wiring density being increased, since a wiring part affects warp significantly, it is necessary to model wiring patterns accurately.
However, since a wiring pitch is made finer, in order to model all wiring patterns in detail, it is necessary to carry out finite element division innumerable times. Thus, it is difficult to model all wiring parts in detail even with the present computer performance.